1. Field of the Invention
The present invention concerns an integrated circuit having a patterned dielectric region that provides good step coverage for subsequently deposited layers.
2. Description of the Prior Art
The use of "field oxides" is a standard technique in integrated circuit design. The field oxide is a patterned region of silicon dioxide that separates various regions of an integrated circuit, to prevent interaction therebetween. One standard technique for forming tthe field oxide is to initially deposit silicon nitride on a silicon semiconductor body, form a lithographic pattern of photoresist on the nitride, and then etch away the regions of the nitride that are unprotected by the photoresist. Then, the silicon regions exposed by the nitride removal are oxidized by exposure to either dry oxygen or steam at an elevated temperature. These grown oxide regions then serve as the field oxide regions. However, this leads to the well-known "birds beak" effect, wherein the grown oxide extends partially under the overlying nitride layer, due to diffusion of oxygen laterally into the silicon body as the oxide is grown. The birds beak effect undesirably increases the area occupied by the isolation region. This is particularly significant as lithographic dimensions decrease, and the relative area occupied by the birds beak increases.
Another known field oxide isolation technique is to deposit silicon dioxide on the semiconductor body, rather than to grow it. The deposited oxide is then directly patterned by photoresist and etched, leaving the desired isolation regions. However, this has the well-known disadvantage of producing steep sidewalls at the edges of the isolation regions. The steep sidewalls are difficult to cover satisfactorily with subsequently deposited layers. This is particularly troublesome with conductive layers that need to provide continuous coverage over the sidewalls, in order to provide electrical connectivity between elements of the integrated circuit. Various techniques have been proposed to smooth the sidewalls. These include techniques for tapering the edge of the sidewall, or to round off the top corner. A review of these techniques is given in "Bilayer Taper Etching of Field Oxides and Passivation Layers", L. K. White, Journal of the Electrochemical Society, vol. 127 L page 268 (1980). A technique proposed in that article is to use a "taper control" layer on top of an oxide layer being isotropically etched in a buffered HF solution. However, the various techniques tend to have problems with reproducibility in many cases. In addition, many of the prior art techniques tend to cause an undesirable increase in the width of the etched region, reducing the number of features that may be placed in a given area.
The use of tapered edges is not limited to field oxide isolation regions. For example, tapered sidewalls of contact windows are produced by a variety of techniques, typically by flowing a doped glass at an elevated temperature.